1. Field of the Invention
The present invention relates to signal path layout and routing and more particularly to binning layout.
2. Description of the Related Art
An integrated circuit typically includes a plurality of generally horizontal layers, each layer having a plurality of components. The components that are to be connected on an integrated circuit form a net, while any component not connected to a particular net is considered to be an obstruction to that net.
One step in the design of an integrated circuit is to select the wire paths to connect the components. The path of the actual connection between the components, known as the wire path, is then defined as the route via which the components are connected.
It is known to use routing tools to provide the path for the actual connection between the components. However, arbitrary routing, as generated by known routing tools, often does not allow the prediction of cross-coupling (i.e., noise) between wire paths and propagation delays (i.e., timing) within a wire path. Instead a post routing analysis is often performed to check noise and timing, after which the routing may need to be changed iteratively to address any noise or timing issues that are identified by the post routing analysis.
After the routing adjustment, the design analyses and corrective actions are iteratively performed on the integrated circuit routing until all or most noise and timing issues have been addressed. To avoid problems related to cross-coupling, many designs use shield wires to shield signal wires from aggressors. Shield wires may also provide a grid to deliver power efficiently to the entire integrated circuit design.
Known routing tools are often blind to power distribution requirements of the design. Known routing tools might create dense routing regions with no room for the power grid or might route poorly by leaving space to compensate for a power grid. These known routing tools often do not allow alternate assignment for even power distribution. Additionally, these routing tools might produce a routed design in which there may not be enough available channel area to insert decoupling capacitors.
Accordingly, it is desirable to provide a methodology which enables a correct by construction physical layout design. Such a methodology would reduce design turnaround and makes the outcome of a routed design more predictable.